Crate riscv

Low level access to RISC-V processors

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.59 and up. It might compile with older versions but that may change in any new patch release.

Features

This crate provides:

• Access to core registers like mstatus or mcause.
• Interrupt manipulation mechanisms.
• Wrappers around assembly instructions like WFI.

Optional features

critical-section-single-hart

This feature enables a critical-section implementation suitable for single-hart targets, based on disabling interrupts globally.

It is unsound to enable it on multi-hart targets, and may cause functional problems in systems where some interrupts must be not be disabled or critical sections are managed as part of an RTOS. In these cases, you should use a target-specific implementation instead, typically provided by a HAL or RTOS crate.

Modules

asm

Assembly instructions

delay

Delay devices and providers

interrupt

Interrupts

register

RISC-V CSR’s

Macros

singleton

Macro to create a mutable reference to a statically allocated value